1. Field of the Invention
The present invention generally relates to analog-to-digital (A/D) converters and, more particularly, to a new architecture to realize fast, high resolution A/D converters in high-reliability VLSI monolithic semiconductor technology.
2. Description of the Prior Art
In many digital signal processing applications, it is necessary to accept signals that originate in the analog domain and to convert them to digital form prior to processing. As very large scale integrated (VLSI) circuit technology matures, digital signal processing is increasingly employed to address many low cost but high performance applications. It thus becomes crucial to implement analog/digital interface functions at low power, high precision and high reliability, either as discrete monolithic semiconductor devices or as on-chip macrocells for VLSI signal processors.
Many signal processing systems for military, industrial and nuclear applications require high-speed, high-resolution A/D converters in their front-end or input circuitry. These converters demand a high sensitivity and linearity of at least 12 bits at megaHertz (MHz) sampling rates. Present approaches to the realization of such converters depend on hybrid and discrete components that are bulky, cumbersome and expensive. More specifically, previous approaches to achieving high-speed, high-resolution monolithic A/D converters have used fully-parallel, two-step flash or pipelined architectures.
A fully parallel A/D converter architecture is described in an article entitled "A Fully Parallel 10 Bit A/D Converter with Video Speed: by Toyoki Takemoto, Michihiro Inoue, Hideaki Sadamatsu, Akira Matsuzawa, and Kazuhiko Tsuji in IEEE Journal of Solid-State Circuits, vol. SC-17, no. 6, pp. 1133 to 1138 (Dec. 1982). The fully parallel architecture described requires 2.sup.m -1 comparators to achieve m bits of resolution.
A two-step flash A/D converter architecture is described in an article entitled "An 8 MHz CMOS Subranging 8-Bit A/D Converter" by Andrew G. F. Dingwall and Victor Zazzu in IEEE Journal of Solid-State Circuits, vol. SC-20, no. 6, pp. 1138 to 1143 (Dec. 1985). The two-step flash architecture described requires 2.sup.1+ (m/2)-1 comparators to achieve m bits of resolution.
In both the fully parallel and two-step flash architectures, the large number of required comparators as well as their associated peripheral circuits result in large die sizes along with significant input loading and power dissipation, making their extension to high resolution (more than 10 bits) difficult or impractical. A pipelined architecture is described in "A Pipelined 5-M sample/s 9-bit Analog-to-Digital Converter" by Stephen H. Lewis and Paul R. Gray in IEEE Journal of Solio-Statc Circuits. vol. SC-22, no. 6, pp. 954 to 961 (Dec. 1987). The pipelined architecture does not suffer from large die sizes; however, the stringent requirement of interstage differential amplifiers for analog subtraction and amplification tends to limit its speed and accuracy, particularly when implemented in bulk complementary metal-oxide-semiconductor (CMOS) switched capacitor circuitry. These limitations have generally held previous approaches for achieving improved A/D converters to a maximum resolution of ten bits or less at 5 to 10 MHz sampling rates.
Translating these approaches to monolithic implementation requires innovative analog switched capacitor circuitry as well as efficient self-calibration techniques. Presently, these desirable items are being actively pursued by various industrial and university researchers; however, there remains a need for facile implementation of monolithic A/D converters with more than 12-bit resolution at higher than 10 MHz sampling rates.